In the design of digital circuitry, it is common that two functional blocks operating in two different timing domains wish to communicate with one another. This is typically performed in a master/slave transaction involving three steps:
i) the master unit initiates a request to the slave unit, PA0 ii) the slave unit detects the request, and services it, and PA0 iii) the slave unit indicates completion of the task by returning an acknowledgement to the master unit. PA0 a) said first system issuing a transaction request over said communication link to said second system as a result of a clock edge in said first timing domain; PA0 b) said second system accepting said transaction request as a result of a clock edge in said second timing domain, said acceptance of said transaction request being communicated to a phase synchronization state machine within said second system and to a transaction state machine within said second system; PA0 c) said transaction machine processing said transaction request and said phase synchronization machine counting the number of clock cycles in said second timing domain during the processing of said transaction; PA0 d) upon completion of said transaction, said second system generating an acknowledge signal to be transmitted from said second system to said first system over said communication link as a result of a clock edge in said first timing domain, said synchronization being achieved by said phase synchronization machine using said predetermined relation between said different clock speeds in order to determine allowable clock periods of the second timing domain to transmit said acknowledge signal to said first timing domain.
In situations where the master and slave units have no common timing reference, i.e. the system clocks of the respective functional blocks are operating at different speeds, it is essential to ensure that the signals passed between master and slave units are not misinterpreted. Such misinterpretations can occur where signals are asserted by the master unit during the set-up and hold period of input logic of the slave unit. For example, the input signal to slave unit logic should not change for a small period of time both before, and after, the valid clock edge of the slave timing domain. If such a situation does occur, then the output of the input logic to the slave unit will be uncertain, and metastability of the slave unit input logic can occur.
A known technique in avoiding this problem is to use dual rank synchronization. In this technique, a catching cell is used at the input to the slave unit, S, and an example of this is shown in FIG. 1.
In FIG. 1 there is shown a master unit 10 coupled to a slave unit 20 by means of communication lines 18, 19. Master unit 10 has an internal clock CK.sub.M, and slave unit has an internal clock CK.sub.S. The time taken for a transaction signal request (REQ) generated by master unit 10 to reach the input of a transaction machine 22 in slave unit 20 over request line 18 is thus variable, lying between the extremes of two cases. If the signal generated by an output flip-flop 14 in master unit 10 reaches flip-flop 24 immediately prior to the set-up time of flip-flop 24, then the signal will be propagated through to flip-flop 25 at the first slave clock edge thereafter, and will be propagated through to the output of flip-flop 25 at the second slave clock edge thereafter. The transfer time is thus approximately one clock period in the slave timing domain.
Alternatively, the signal generated by flip-flop 14 reaches flip-flop 24 during or after the set-up and hold time, and the signal is not propagated through to the input of flip-flop 25 until the second slave clock edge. (Any metastability which may have resulted from the asynchronous input to flip-flop 24 will by then have been resolved.) The signal will then be propagated through to the output of flip-flop 25 after the third slave clock edge. The transfer time is thus approximately two clock periods of the slave timing domain.
The signal received by transaction machine 22 may be acknowledged by returning an acknowledge signal (ACK) on line 19, via output flip-flop 26, and is received by a master unit transaction machine 12 in similar manner using flip-flops 15,16.
For a total transaction, including the return of the acknowledge signal back into the master timing domain, the total time is a maximum of 2.times.(slave clock period+master clock period)+transaction processing time in the slave functional block. Everything other than the transaction processing time in the slave unit is an overhead. There is a requirement to reduce this overhead in the total transaction time to a minimum.